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Power Supply Network Design: a Case Study Driven Approach : Volume 5, Issue 12 (13/06/2007)

By Eireiner, M.

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Book Id: WPLBN0003973716
Format Type: PDF Article :
File Size: Pages 6
Reproduction Date: 2015

Title: Power Supply Network Design: a Case Study Driven Approach : Volume 5, Issue 12 (13/06/2007)  
Author: Eireiner, M.
Volume: Vol. 5, Issue 12
Language: English
Subject: Science, Advances, Radio
Collections: Periodicals: Journal and Magazine Collection (Contemporary), Copernicus GmbH
Historic
Publication Date:
2007
Publisher: Copernicus Gmbh, Göttingen, Germany
Member Page: Copernicus Publications

Citation

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Missal, T., Schmitt-Landsiedel, D., Berthold, J., Henzler, S., & Eireiner, M. (2007). Power Supply Network Design: a Case Study Driven Approach : Volume 5, Issue 12 (13/06/2007). Retrieved from http://community.worldlibrary.net/


Description
Description: Institute for Technical Electronics, Technical University Munich, Germany. A study, based on product related scenarios, on power supply integrity issues is conducted. The effectiveness of specific design parameters depends strongly on the expected loading of the power distribution grid. Therefore, the commonly used approach to only use an even current distribution can lead to non-optimal power grid designs. For power grid optimization, a problem reduction from quadratic to linear order is presented. Simulations in a System-on-Chip (SoC) environment show, that power supply integrity mainly depends on the placing of the cores within the SoC die.

Summary
Power supply network design: a case study driven approach

Excerpt
Benoit, M., Taylor, S., Overhauser, D., and Rochel, S.: Power Distribution in High-Performance Design, in: Proceedings of IEEE Symposium of Low-Power Electronics Design, 274–278, 1998.; ITRS: International Technology Roadmap for Semiconductors, http://public.itrs.net/, 2005.; Dharchoudhury, A., Panda, R., Blaauw, D., and Vaidyanathan, R.: Design and Analysis of Power Distribution Networks in PowerPC Mircoprocessors, in: Proceedings of Design Automation Converence, 738–743, 1998.; Larsson, P.: Power Supply Noise in Future IC's: A Crystal Ball Reading, in: IEEE Custom Integrated Circuits Conference, 467–474, 1999.; Lueftner, T., Berthold, J., Pacha, C., Georgakos, G., Sauzon, G., Hoemke, O., Beshenar, J., Mahrla, P., Just, K., Hober, P., Henzler, S., Schmitt-Landsiedel, D., Yakovleff, A., Klein, A., Knight, R., Acharya, P., Mabrouki, H., Juhoor, G., and Sauer, M.: A 90 nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor with 380 MHz ARM9 and Mixed-Signal Extensions, in: 2006 ISSCC Digest of Digital Papers, 252–253, 2006.; Mezhiba, A V. and Friedman, E G.: Scaling Trends of On-Chip Power Distribution Noise, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12, 386–394, 2004.; Nassif, S R. and Fakhouri, O.: Technology Trends in Power-Grid-Induced Noise, in: Proceedings of the 2002 international workshop on System-level interconnect prediction, 55–59, ACM Press, 2002.; Saint-Laurent, M. and Swaminathan, M.: Impact of Power-Supply Noise on Timing in High-Frequency Microprocessors, IEEE Transactions on Advanced Packaging, 27, 135–144, 2004.

 

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